Diz 31 en

Z DCEwiki
Přejít na: navigace, hledání

Implementation Methods of LD-RLS with Directional Forgetting for Embedded Systems on a Chip[editovat]

Author: Roman Bartosinski

Disertační práce 2011

Download thesis in PDF

The thesis deals with an implementation of the recursive least squares (RLS) based on the LDU decomposition (LD-RLS) with directional forgetting. Today's implementations of adaptive algorithms for embedded systems use mainly the least mean square (LMS) algorithms for their simplicity and low computational complexity which result in high speed and throughput. RLS algorithms aren't so often used for their higher computational complexity. The LD-RLS algorithms can be attractive for control applications to identify an unknown system or to track time-varying parameters. Solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers the possibility to use a priori information about the identified system and its parameters. Directional forgetting (DF) is an alternative to exponential forgetting (EF). DF was devised 25 years ago, but it is completely omitted in current implementations of RLS algorithms. It's meant mainly for more complicated computation and thus higher computational complexity. It is omitted despite it ensures more robust identification in systems with insufficiently excited inputs. A possible implementations of the EF LD-RLS and DF LD-RLS algorithms were discussed in the thesis. Implementations for a systolic array were discussed to demonstrate the high data dependences in LD-RLS algorithms. The second architecture was used for the implementation of LD-RLS algorithms. It is based on the UTIA DSP platform which has been developed recently at the department of Signal Processing, ÚTIA AV ČR. The platform is designed to be a highly reconfigurable hardware accelerator for systems on a chip based on FPGAs. The thesis describes the extension of the platform with new features for implementation of DF LD-RLS. Another objective in the thesis is to improve the implementation methodology for the platform. Automatic code generation was developed and used to speed up the development process of implementation algorithms on the platform. Finally,the EF LD-RLS and DF LD-RLS algorithms were implemented in the hardware and compared with corresponding versions in software.

Diz 2011 bartosinski roman.pdf
Diz 31 trpisovsky tomas.pdf
Diz 31 vaclavek pavel.pdf
Diz 31 vrba radimir.pdf