Bp 87 en
Automatic VHDL code generation for FPGA
Author: Tomáš Novák
Nowadays, Digital Signal Processing (DSP) has a great significance. Usage of common processors is often ineffient due to their only sequential operating. Another posibility is to use signal processors, but the achieveable parallelism isn't great. The best way is to use Field Programmable Arrays (FPGAs) together with optimal scheduling. This thesis concentrates on automatic VHDL generation from a given optimal schedule of a DSP algorithm. The automatic VHDL generator is a part of the tool ACGM (Automatic Code Generator for Matlab), which deals with scheduling of Matlab-compatible algorithms for FPGA architectures with pipelined arithmetic units. The thesis describes the architecture designed for implementation of DSP algorithms on FPGAs and how the automatic generator was created.
