Dp 524 en
Hardware Accelerator for brain-machine interface
Author: Beran Vladimír
System design and implementation of IP macros FGPA enabling HW acceleration for BCI calculation is the scope of this theses. This IP macros must be compatible with existing SW and HW. When designing the macros the emphasis is on low power consumption. Techniques to reduce power consumption of digital circuits not only FPGA are discused in the first part theses. The entire system design concept HW BCI is executed in the second part. It also made clear requirements for each macro. Their implementation and verification is described in the last section.