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Optimalization algorithms for FPGA[editovat]

Author: Matějíček David

Diplomové práce 2007

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This thesis is motivated by the need to optimize computation time of Digital Signal Processing (DSP) algorithms designed in Matlab, generate an efficient FPGA implementation and especially reduce total design time. DSP algorithms are often implemented on Field Programmable Gate Arrays (FPGAs), because the FPGA design achieves a high level of parallelism.

The thesis deals with implementation of Automatic Code Generation from Matlab tool, which is part of Torsche Scheduling toolbox for Matlab. This tool generates code for simulation in TrueTime and FPGA design in VHDL.

The primary focus of this thesis is to design a format of input data, implement syntaktical analyser and implement code generator for TrueTime.

Dp 2007 matejicek david.pdf