Dp 231 en

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Processor In the Loop simulation[edit]

Author: Rapavý Martin

Diplomové práce 2007

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This gradution thesis describes the design of the processor in the loop (PIL) simulation support in Processor Expert Embedded Real-Time target, which has been developed by Department of Control Engineering. The advantages of an automatically generated code in the development of a control embedded sofware and the principles of a code generation in Matlab Simulink are discussed in the thesis.

Summary of existing solutions of PIL simulation is mentioned. Possible ways to provide a real-time processor in the loop simulation support are introduced.

The designed solution utilizes Matlab, Simulink, Real-Time Workshop and Processor Expert tools. The architecture of the implemented solution and the cooperation of the tools in the simulation are described.

The potential of the final solution and its usage are presented in the demo task. Results of the model in the loop simulation and the processor in the loop simulation are discussed. The possibilities of a future development are outlined.

Dp 2007 rapavy martin.pdf