Bp 62 en

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Control unit for two-cylinder engine[edit]

Author: Milan Šafránek

Bakalářské práce 2006

Download thesis in PDF

Aim of this bachelors work is to realize digital logical analyzer with FPGA Spartan 3 XC3S1500L. Analyzer should have 16 data inputs and should support the basic function like measuring values in time, visualization of data and support for optional trigger conditions. Prime exit of the device is a standard VGA monitor. Measured data sequences can be save to the flash memory placed on board RC10. Data can be subsequently transfered to the PC for other processing.

Bp 2006 safranek milan.pdf