Difference between revisions of "Dp 524 en"

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* '''Jakub Šťastný''', tel: +420 737 861 687,  mailto:stastnj1@fel.cvut.cz
 
* '''Jakub Šťastný''', tel: +420 737 861 687,  mailto:stastnj1@fel.cvut.cz
  
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Revision as of 00:57, 27 August 2014

Hardware Accelerator for brain-machine interface

Author: Beran Vladimír

Diplomové práce 2014

Download thesis in PDF

System design and implementation of IP macros FGPA enabling HW acceleration for BCI calculation is the scope of this theses. This IP macros must be compatible with existing SW and HW. When designing the macros the emphasis is on low power consumption. Techniques to reduce power consumption of digital circuits not only FPGA are discused in the first part theses. The entire system design concept HW BCI is executed in the second part. It also made clear requirements for each macro. Their implementation and verification is described in the last section.

Dp 2014 beran vladimir.pdf
P 2014 beran vladimir.pdf