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Testing of student's works on finite machines

Author: Dibelka Lukáš

Diplomové práce 2010

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The aim of this diploma thesis is to automatize checking process during committing student's works. It means to create checking experiments for these works and create testing system for providing experiments. Students works will be hardware implementations of asynchronous finite machines, exactly sequence detectors. The aim of proposed checking experiments is to discover if students implementations of finite machines accept language, which is said in their submission. In this work there is description of these experiments and theirs results. Further this work describes control unit implementing these experiments, generator of debugging logic signals, communication interface with simulator environment MATLAB - Simulink and generator of student's excercises. A part of these diploma thesis is appendix with instructions for creating MATLAB model of finite machine of student work.


Dp 2010 dibelka lukas.pdf