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Application for conversion of Timed Automata into a FPGA platform
Author: Jan Breuer
The purpose of this Bachelor’s thesis is to create a converter from one representation of a timed automata to another. The model of the timed automata is created and tested in a UPPAAL tool. The output of the tool is loaded and converted to another language, which is suitable for other work and a subsequent programming to FPGA. As a final language was selected a language of MATLAB. In MATLAB, with the aid of Xilinx System Generator, is created a code for the final platform FPGA.
