/* zynq-mzapo.dts - Xilnx ZYNQ-7000 MZAPO device tree source */ /* * Copyright (c) 2015-2017, 2019, 2021 Wind River Systems, Inc. * Copyright (c) 2022 Michal Sojka * * This file is licensed under the Creative Commons CC0 1.0 Universal Public * Domain Dedication License (CC0-1.0). You may obtain a copy of the License * at: * https://creativecommons.org/publicdomain/zero/1.0/ * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */ /dts-v1/; #include "zynq-7000.dtsi" / { chosen { bootargs = "gem(0,0) f=0x40"; }; amba { uart0: uart@e0000000 { compatible = "xlnx,xuartps"; current-speed = <115200>; reg = <0xE0000000 0x1000>; clock-frequency = <50000000>; interrupts = <59>; interrupt-parent = <&intc>; }; uart1: uart@e0001000 { status = "disabled"; }; ttc_1: ps7-ttc@f8002000 { /* * Don't let VxWorks drive the second TTC. We * will use it with our driver (see below) */ status = "disabled"; }; psr_ttc: psr-ttc@f8002000 { compatible = "cvut,psr-ttc"; reg = <0xf8002000 0x1000>; clock-frequency = <111111111>; interrupt-parent = <&intc>; interrupts = <69 70 71>; }; motor1: pmod1@43c20000 { compatible = "cvut,psr-motor"; /* Register locations */ reg = <0x43c20000 0x1000>, /* FPGA (PWM control, IRC status) */ <0xE000a000 0x1000>; /* GPIO (IRC IRQ) */ interrupt-parent = <&intc>; interrupts = <52>; gpio-irq-bit = <0x04>; }; motor2: pmod2@43c30000 { compatible = "cvut,psr-motor"; /* Register locations */ reg = <0x43c30000 0x1000>, /* FPGA (PWM control, IRC status) */ <0xE000a000 0x1000>; /* GPIO (IRC IRQ) */ interrupt-parent = <&intc>; interrupts = <52>; gpio-irq-bit = <0x40>; }; }; };